This application relies for priority upon Korean Patent Application No. 98-32238, filed on Aug. 7, 1998, the contents of which are herein incorporated by reference in their entirety.
The present invention concerns a semiconductor device. More particularly, the present invention relates to a method of forming isolation trenches in a semiconductor device.
Isolation technology is very important to electrically isolate the elements fabricated in a highly integrated semiconductor device. The local oxidation of silicon (LOCOS) method presently used in the fabrication of 256M bit DRAMs has often shows such drawbacks as the formation of a bird""s beak phenomenon that causes flaws in the active openings, the reduction of a subsequent process margin owing to a reduced field oxide layer, imperfect electrical isolation owing to the reduced isolation distance between the elements, etc. All of these drawbacks can result in poor electrical characteristics for the memory device.
One alternative is to form the field oxide layer by means of an oxidation process. In this case, the semiconductor substrate is etched to form shallow trenches having a required depth, and the trenches are filled with an oxide layer by means of chemical vapor deposition (CVD). This is called shallow trench isolation technology. FIGS. 1A to 1E illustrate the steps of forming isolation trenches for a parasitic transistor at the top edge portions of an isolation trench.
Referring to FIG. 1A, a pad oxide layer 12, a nitride layer 14, a high temperature oxidation (HTO) layer 16, and an anti-reflective coating (ARC) 18 are sequentially deposited over a semiconductor substrate 100. The pad oxide layer 12 is preferably deposited by a thermal oxidation process. The ARC 18 stabilizes the size of the photoresist pattern, securing the process margin.
Then, a patterned masking photoresist 20 is formed over the ARC 18 so as to define active and non-active regions, as shown in FIG. 1B. The ARC 18, HTO layer 16, nitride layer 14, and pad oxide layer 12 are sequentially etched by dry etching according to the patterned masking photoresist 20, so as to attain a masking pattern. Removing the photoresist 20 and ARC layer 18, the HTO layer 16 is used as a trench patterned masking layer to dry-etch the trench 22 in the semiconductor substrate 10.
A thermal oxidation layer 24 is deposited over the bottom and side walls of the trench 22 to cure the parts damaged during the etching of the trench 22, as shown in FIG. 1C.
As shown in FIG. 1D, an oxide layer 26 is subsequently deposited over the HTO layer 16 and the trench 22. The oxide layer 26 is preferably formed of an undoped silicon glass (USG) or O3-TEOS (Ozone-Tetraethylorthosilicate), preferably by a plasma CVD process. The oxide layer 26 preferably has a good gap-fill characteristic.
A PE-TEOS (Plasma Enhanced-Tetraethylorthosilicate) layer 28 is deposited over the oxide layer 26. Then, the substrate is annealed at a temperature of preferably more than 900xc2x0 C. in order to prevent the excessive recessing of the oxide layers 26 and 28 in a subsequent CMP process.
The PE-TEOS layer 28, oxide layer 26, and HTO layer 16 are polished to a plane by means of CMP process until a part of the thickness of the nitride layer 14 is exposed, thus forming an isolation trench.
As shown in FIG. 1E, the nitride layer 14 and the pad oxide layer 12 are then sequentially removed from the sides of the trench by dry or wet etching. A masking oxide layer (not shown) is deposited on the sides of the isolation trench in the substrate 10 in order to selectively implant impurity ions into the upper surface of the substrate 10 to produce well regions, field regions, and channel stop regions. The masking oxide layer serves as a buffer to protect the substrate when performing the ion implantation. After removing the masking oxide layer, a thin gate oxide layer 32 is then deposited over the substrate 10 and the insolation trench.
However, in this case, the active region of the substrate 10 at top edges is in contact with the oxide layer 26 of the isolation trench 22, as indicated by reference numeral 30 in FIG. 1E. This acts to generate a parasitic transistor and an electric field from the isolation trench to the active region. This causes drain-induced barrier lowering (DIBL), a reverse narrow-width effect that lowers the threshold voltage of the element, and causes the generation of spurious transistors.
It is an object of the present invention to provide a method of forming isolation trenches in a semiconductor substrate, while preventing the generation of spurious transistors in the upper edges of the trenches.
The present invention provides isolation trench structures having a rounded profile at top edges so as to suppress parasitic transistor generation. The rounding profile at the top edges of the active region is achieved by undercutting the pad oxide layer during fabrication. Undercutting the pad oxide layer exposes a top surface of the active portion of the substrate. The exposed active substrate is then rounded during the etching of the substrate to form an isolation trench.
More specifically, according to an embodiment of the present invention, a method of forming an isolation trench in a semiconductor substrate, comprises forming a first insulating layer over the substrate, forming a second insulating layer over the first insulating layer, etching the first and second insulating layers to define active and non-active regions according to a patterned masking photoresist layer, etching a first portion of the substrate in the non-active region, undercutting the first insulating layer in the active region to expose second portions of the substrate in the active region, etching the substrate using the second insulating layer as a masking layer to form a trench in which exposed edges of the substrate are rounded, forming a third insulating layer on the bottom and side walls of the trench and over the rounded edges of the substrate, and etching the third insulating layer to expose the second insulating layer. The method may also comprise removing the first and second insulating layers.
The first insulating layer is preferably an oxide layer having a thickness of about 70 xc3x85 to 240 xc3x85. The third insulating layers is preferably an oxide layer having a thickness of about 100 xc3x85 to 500 xc3x85. The second insulating layer preferably comprises a silicon nitride layer and a high temperature oxidation (HTO) layer, in which the second insulating layer is about 1500 xc3x85 thick and the high temperature oxidation layer is about 500 xc3x85 thick.
The method may further comprise depositing an anti-reflective coating (ARC) over the second insulating layer. The anti-reflective coating preferably has a thickness of about 600 xc3x85.
The first portion of the substrate is preferably etched to a thickness in the range of about 200 xc3x85 to 500 xc3x85. The amount undercut of the first insulating layer is preferably about 100 xc3x85 to 300 xc3x85.
The present invention will now described more specifically with reference to the drawings attached only by way of examples.